Faculty of Engineering and Natural Sciences · Computer Engineering · Undergraduate
Course Objective
Introduces the basic concepts of computer organization.
Course Content
Integrated Circuits, Solvers, Selectors, Registers, Data Bus, Memory Transfer Language, ALU, Addressing Methods, Memory-Addressing Instructions, Instruction Code, Timing and Control, Control Unit Design, ASM, RISC/CISC. العربي
Required Resources
Computer System Archtitectures – M. Morris Mano
Recommended Resources
Computer Organization and Architecture Designing for Performance – William Stallings,
Lecture Notes
Explanations
The assessment will consist of a quiz, a midterm and a comprehensive final exam.
1. The date of the quizzes is as announced in the table. The content will be all topics of the previous weeks. There is no make-up for the quizzes in any way.
2. Other exam dates are as announced in the table.
3. Midterm exam topics cover all topics covered until the exam week. The final exam covers the topics covered throughout the semester. Midterm and Final exam dates, time and place will be announced by the Dean's Office.
4. Participation in the course does not mean attendance (attendance). In the courses that will be taught interactively, questions will be asked to the students and individual evaluation will be made on the answers from the students.
Rules
1. Attendance: According to the Regulation, if a student does not attend 30% of the total course hours, he/she will receive an absentee grade (DZ) and fail the course.
2. Getting Help: It is important for your education that you ask your questions about the course during the class or during the meeting hours and learn the subject in a timely manner. We encourage our students to seek help by asking questions when necessary.
3. Academic honesty: The work that will be the subject of the course grade is expected to be entirely your own effort and work. In unethical cases such as plagiarism, copying, etc., you will be subject to disciplinary investigation and penal sanctions in accordance with the relevant regulation of IZU. Works found to be copied will be graded accordingly.
4. Exam Evaluation: If deemed necessary, an oral exam will be held after the written exams are evaluated. The results of the oral exam will determine the written exam grades.
5. The assessments specified in this syllabus are fixed and no extra compensatory assessment will be made to raise the grade.
Core Area Distribution
Teaching Methods
Assessment & Evaluation
ECTS / Workload
| Activity | Quantity | Duration (h) | Total Workload |
|---|---|---|---|
| Course Duration (Including Exam Week) | 15 | 3 | 45 |
| Out of Class Study Period | 15 | 6 | 90 |
| Midterm | 1 | 2 | 2 |
| Quiz | 1 | 1 | 1 |
| Assignment | 0 | 0 | 0 |
| Practice | 0 | 0 | 0 |
| Final | 1 | 2 | 2 |
Course Schedule
| Week | Subject | Preparation |
|---|---|---|
| 1 | Introduction, Combinational Circuits, Decoders, MUX | Section 1: Digital Logic Circuits Section 2: Digital Elements |
| 2 | Registers, Counters, Memory Unit) | Section 2: Digital Elements Section 3: Data Representation |
| 3 | RTL, BUS and Memory Transfers | Section 4: Register Transfer and Micro Operations |
| 4 | Arithmetic, Shift Operations, ALU | Section 4: Register Transfer and Micro Operations |
| 5 | Memory-Reference Instructions | Section 5: Basic Computer Structure and Design |
| 6 | Instruction Codes, Timing and Control, Instruction Cycles | Section 5: Basic Computer Structure and Design |
| 7 | Design of Basic Computer | Section 5: Basic Computer Structure and Design |
| 8 | Midterm Exam | Midterm Exam |
| 9 | Programming the Basic Computer | Section 6: Basic Computer Programming |
| 10 | Micro Programmed Control, Address Sequencing | Section 7: Micro Programmed Control |
| 11 | Design of Control Unit | Section 7: Micro Programmed Control |
| 12 | Stack Organization, Reversh Polish Notation | Section 8: Central Processing Unit |
| 13 | Algorithmic State Machines | Section 8: Central Processing Unit |
| 14 | RISC / CISC | Section 8: Central Processing Unit |
| 15 | Cache Memory | Section 12: Memory Design |
| 16 | Final Exam | All Lectures |